Formal Verification Engineer

  • Position Type: Contract
  • Location: San Francisco

Required Skills and Experience:
● Strong fundamentals in digital ASIC verification; experience using Verilog.
● Strong Formal background/experience using FV techniques to verify complex CPU and SOC micro-architectures.
● Experience in writing assertions in SVA
● Strong programmable language experience is required (one or more of Verilog, SystemVerilog, Perl, Python, Tcl Scripts, Makefile and/or C++)
● A good understanding of the complete verification life cycle
● Proficiency in UVM
● Domain knowledge in one or more of these areas: CPU, fabric, memory
controller, encryption, caches, coherence, MMU, high speed interfaces/protocols

Roles and Responsibilities:
● Define verification architecture, develop test plans and build verification
environment
● Work with design team to understand design intent and bring up verification plans
and schedules
● Verify using advanced verification methodologies
● Assist in emulation, FPGA, prototyping efforts
● Assist in silicon bring-up, debug and characterization
● set up methodologies, come up with verification plans, and verify the design meets the highest quality standards.