SoC/Arm Compliance

  • Position Type: SoC/Arm Compliance
  • Location: San Francisco

Required Skills and Experience: 

Strong fundamentals in digital ASIC verification

  • Multiple project experience in coherent interconnect and multi-core system verification
  • Familiarity with CHI, ACE, or other equivalent coherent interconnect protocol, system memory hierarchy, and multi-core SOC designs
  • Strong programmable language experience is required (one or more of Verilog, SystemVerilog, Perl, Python, Tcl Scripts, Makefile and/or C++)
  • Expertise in the verification of coherent, high speed cache controllers
  • Strong understanding of ordering rules in a multi-core system
  • Strong understanding of fabric topologies and related performance issues
  • A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
  • Extensive knowledge in multiple testbench structures
  • Knowledge of FPGA and emulation platforms
  • Proficiency in UVM, C/C++
  • Experience w/ PSS or higher level test construction languages
  • Knowledge of assertion-based formal verification

 

Roles and Responsibilities:

  • Focus on Coherent Fabric verification to understand the internal requirements and complexities of our SOC system and architect the required verification strategy.
  • Set up methodologies, come up with test plans, and verify that the design meets the highest quality standards.
  • Participate in architecture/product definition through early involvement in the product life-cycle.
  • Define entire verification architecture for all system memory coherency aspects
  • Deep dive into microarchitecture of all agents and subsystems involved with system coherency
  • Define verification architecture, develop test plans and build verification environment
  • Work with design team to understand design intent and bring up verification plans and schedules
  • Verify Subsystems and Full SoC using advanced verification methodologies
  • Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard
  • Debug test cases and report verification result to achieve expected code/functional coverage goal
  • Assist in emulation, FPGA, prototyping efforts
  • Assist in silicon bring-up, debug and characterization