Education: All candidates MUST hold a Bachelor’s degree (or higher) in Engineering.
Experience: 14+ Years
- Minimum of 14 years experience in Digital ASIC verification with at least 5 years focused on UVM
- Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using SystemVerilog.
- Experience with design architecture and detailed specification generation.
- Experience with UVMf
- Experience with hardware emulators (Palladium, Veloce)
- Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
- Ability to write executable test plans
- Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
- Ability to create self-checking and reusable testbenches from scratch
- Experience developing Functional Coverage Models and Closing Code Coverage
- Proficient in scripting languages: Make, Perl, Python, etc.
- Revision Control Systems: svn, cvs, git
- Proficient in Linux Environments
- Demonstrated history of 1st pass success with ASIC designs.
- Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable testbenches from scratch
- Develop Functional Coverage Models and Closing Code Coverage
- Utilize UVM to create drivers, monitors, predictors, and scoreboards
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